Traffic aware routing in 3D NOC using interleaved asymmetric edge routers, Journal of Nano CommunicationNetworks, Elsevier 2021
Enhancement and modeling of drain current in negative capacitance double gate TFET, Silicon, 2021
Human context recognition with reduced feature space vectors for resource constraint gadgets, J. Math. Comput. Sci. , 2020
“An Improved Tunnel Field Effect Transistor With L Shaped Gate And Channel”, Journal of Computational Electronics, Springer 2020
“A GA Based Simple and Efficient Technique to Design Combinational Logic Circuits using Universal Logic Modules”, Journal of Circuits, systems and Computers , 2016
" Proposed Hybrid model to detect and prevent SQL Injection ", International Journal of Computer Science and Information Security, 2016
SQLI-Dagger, a Multilevel Template based Algorithm to Detect and Prevent SQL Injection, IJCA, 2016
A Simplified Efficient Technique for the Design of Combinational Logic Circuits, I.J. Intelligent Systems and Applications, 2015
Decimal Floating Point Multiplication using RPS Algorithm, International Journal of Computer Applications® (IJCA), 2011
“RNS based Programmable Decimation Filter for Multi-Standard Wireless Transceivers”, ECTI Transaction on Electrical Engineering, Electronics and Communications, ECTI–EEC Transactions, Special Issue on Communication, 2008
Impact Analysis of Communication Overhead in NoC Based DNN Hardware Accelerators, INDICON, 2022
Smartphone based Human Activity Recognition using RNN variants, INDICON, 2022
RIBiT – Reduced Intra-flit Bit Transitions for Bufferless NoC, VLSI-SoC, 2022
Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks, Proceedings of the Great Lakes Symposium on VLSI 2022, 2022
Analysis Of Routing Algorithms In Bufferless 3d Mesh NoC, ICSTII, 2022
Network On Chip Based Deep Neural Network Accelerators, ICSTII, 2022
Time Domain Data Augmentation Transform With Window Warping In Activity Recognition, ICSTII, 2022
Enhanced Performance of TFET Through Dual Material Gate Coupling, ICSTII, 2022
DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks, Proceedings of the Great Lakes Symposium on VLSI 2022, 2022
Interleaved Edge Routing in Buffered 3D Mesh & CMesh NoC, International Conference on Smart Computing and Communcations, 2021
RESEARCH PROJECTS
"“System Level Analysis and Design of Re-configurable Multi-standard Sigma Delta Analog to Digital Converters for next generation of Wireless transceivers”" ( KSCSTE (Kerala State Council for Science, Technology)- 2013 -2016 , Total outlay Rs.948000)
"Performance Enhancement of Bufferless Routers for 2D Mesh Network-on-Chips" (TEQIP III- 2018 -2020 , Total outlay Rs.100000)
"MODROBS for VLSI Lab" (AICTE- 2020 -2021 , Total outlay Rs.1208000)
"Power reduction by switching activity minimization in 2 Dimensional Mesh Network-On-Chip" ( KSCSTE (Kerala State Council for Science, Technology)- 2020 -2020 , Total outlay Rs.10000)
"Mission 100kft" (TEQIP III- 2020 -2021 , Total outlay Rs.200000)
"Cost Effective Home automation and Monitoring" (TEQIP III- 2020 -2021 , Total outlay Rs.10000)
"Swarm Robotics" (TEQIP III- 2020 -2021 , Total outlay Rs.20000)
"Self Driving Car withdeep learning based real time image recognition and localization" (TEQIP III- 2020 -2021 , Total outlay Rs.30000)
"Autonomous synthetic swarms of drones " (TEQIP III- 2020 -2021 , Total outlay Rs.50000)
