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Dr. NALESH S

Assistant Professor

Department of Electronics

Cochin University of Science and Technology
Kochi - 682022, Kerala, India

E-mail-

nalesh@cusat.ac.in



BRIEF BIO
Dr. Nalesh S is Assistant Professor at Department of Electronics at CUSAT. He received his B.Tech in ECE from NIT Calicut in 2003 after which he worked as Systems Engineer in Wipro Technologies. He completed his M.Tech from IIT Delhi in 2010 and then joined Brocade Communications, Bangalore as ASIC Engineer. In 2012, he joined as research scholar under the supervision of Prof. S K Nandy at CadLab, IISc, Bangalore and received his PhD in 2018. Dr. Nalesh has around 7 years industrial experience in the domain of Embedded Systems, ASIC Front End Design and FPGA Design. His academic and research career spans more than 10 years. His research interests are in the area of AI on Edge, Neuromorphic Computing, Hardware Accelerators, Intelligent Sensors and AI for Healthcare and has supervised multiple projects and published multiple papers in leading international journals and conferences in these domains.

RESEARCH INTERESTS
AI on Edge, Hardware Accelerators, Intelligent Sensors, Monocular Vision, Neuromorphic Computing

RESEARCH PROFILES
Publons : https://publons.com/researcher/3745868/nalesh-s/
Google Scholar : https://scholar.google.com/citations?user=6amr1gUAAAAJ&hl=en

JOURNAL PUBLICATIONS (RECENT) [TOTAL PUBLICATIONS : 9]
  • Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects, Alexandria Engineering Journal, Vol. 91, 2024

  • A physically unclonable function architecture with multiple responses on FPGA, International Journal of Embedded Systems , 2023

  • Efficient CNN Accelerator on FPGA, IETE Journal of Research, Taylor & Francis Vol. 66, 2020

  • High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE 2019

  • Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme, IET Computers & Digital Techniques, 2018

  • Hardware Architecture for Radial Basis Function Neural Network Classifier, IEEE Transactions on Parallel and Distributed Systems, 2018

  • Energy aware synthesis of application kernels through composition of data-paths on a CGRA, Integration, the VLSI Journal, 2017

  • Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture, Journal of Low Power Electronics , 2015

  • A framework for post-silicon realization of arbitrary instruction extensions on recongurable data-paths, Journal of Systems Architecture - Embedded Systems Design, 2014

  • CONFERENCE PUBLICATIONS (RECENT) [TOTAL PUBLICATIONS : 23]
  • MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles, 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), 2023

  • Adiabatic Physical Unclonable Function Using Cross-Coupled Pair, 2022 IEEE International Symposium on Smart Electronic Systems (iSES), 2022

  • Accelerators for Sparse Matrix-Matrix Multiplication: A Review, 2022 IEEE 19th India Council International Conference (INDICON), 2022

  • Implementation of STDP for Spintronics based SNN using 90nm CMOS Technology, 2022 IEEE 19th India Council International Conference (INDICON), 2022

  • A Proof-of-concept Portable, Non-invasive, and Wireless device for the Preliminary Diagnosis of Preeclampsia, 2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2022

  • A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA, 25th International Symposium on VLSI Design and Test (VDAT), 2021

  • Hardware Acceleration of SpMV Multiplier for Deep Learning, 25th International Symposium on VLSI Design and Test (VDAT), 2021

  • Fast Booth Multipliers Using Approximate 4: 2 Compressors, 2021 IEEE International Symposium on Smart Electronic Systems (iSES)(Formerly iNiS), 2021

  • Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA, IEEE 34th International System-on-Chip Conference (SOCC, 2021

  • Efficient hardware acceleration of convolutional neural networks, 32nd IEEE International System-On-Chip Conference (SOCC) 2019,, 2019

  • PATENT
  • A METHOD FOR IMPLEMENTING CONVOLUTIONAL NEURAL NETWORKS USING WINOGRAD MINIMAL FILTERING AND GEMM - Applied,2018