Enhancing Pregnancy Care: Harnessing Label-Free Immunosensors for Pre-Eclampsia Detection Using PdNPs/Poly(3,5-Diaminobenzoic Acid) Modified Glassy Carbon Electrodes, ChemistrySelect, 2024
High-Performance Multi-level Cell Design Using Reduced Retention Time Spintronics Device, Electrica EISSN 2619-9831, AVES 2024
TiCoSb Heusler alloy-based magnetic tunnel junction for efficient computing in memory architecture, Journal of Computational Electronics, Springer 2024
Accelerating Cryptographic Algorithms on RISC-V cores using Carryless Multiplication, Works in Progress in Embedded Computing Journal (WiPiEC Journal), Vol. 10, 2024
Optimizing Free Layer of Magnetic Tunnel Junction for True Random Number Generator, Memories - Materials, Devices, Circuits and Systems, Elsevier Vol. 5, 2023
ACR: APPLICATION AWARE CACHE REPLACEMENT FOR SHARED CACHES IN MULTI-CORE SYSTEMS, , 2019
SkipCache : application aware cache management for chip multi processors, IET Computers & Digital Techniques, IET Comput. Digit. Tech. Vol. 9, 2015
Stochastic Spintronics Device Based Bayesian Networks for Eff icient Uncertainty Modeling, Intentional Conference on Very Large Scale integration (IFIP/ IEEE VLSI-SoC), 2024
B-box: An Efficient and Configurable RISC-V Bit-Manipulation IP Generator, International Symposium on VLSI Design and Test (VDAT-2023), 2023
True Random Number Generator based on Voltage-Gated Spintronic structure, International Conference on VLSI Design ( VLSID 2023), 2023
A Proof-of-concept Portable, Non-invasive, and Wireless device for the Preliminary Diagnosis of Preeclampsia, IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2022
Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V, IEEE International Conference on VLSI Design (VLSID 2021), 2021
2L-2D Routing for Buffered Mesh Network-on-Chip, International Symposium on VLSI Design and Test (VDAT 2019), 2019
SAMO: Store Aware Memory Optimizations, ACM International Conference on Computing Frontiers, 2014
An application-aware cache replacement policy for last-level caches, International Conference on Architecture of Computing (ARCS), 2013
SkipCache: Miss-rate Aware Cache Management, IEEE/ACM 2012 International Conference on Parallel Architectures and Compilation Techniques, 2012
Way sharing set associative cache architecture, IEEE International Conference on VLSI Design (VLSID 2012), 2012
RESEARCH PROJECTS
"Portable device for the Preliminary Diagnosis of Preeclampsia" (DST- 2022 -2023 , Total outlay Rs.2444083)
"Design and Development of a Robot Controller for Synchronized Cooperative Control of Heterogenous Industrial Robot Arms" (RUSA- 2023 -2025 , Total outlay Rs.5916000)
"DSP and AI workload tuned Embedded RISC-V Processors" (MeitY- 2023 -2026 , Total outlay Rs.24800000)
